1. Field of the Invention
The present invention relates to a self-alignment type bipolar transistor which is built in a semiconductor integrated circuit device and a method of manufacturing the same.
2. Description of the Related Art
With the recent growth of an information-oriented society, development of a computer capable of processing a large amount of information at a higher speed is being demanded.
In order to develop such a computer, it is necessary to achieve a high speed in a semiconductor integrated circuit device which is one of important components in point of the function of a computer, and it is further required for that purpose to achieve a high speed of transistors forming the semiconductor integrated circuit.
FIG. 1 is a structural explanatory view of a conventional self-alignment type bipolar transistor.
In FIG. 1, a reference numeral 1 represents an n.sup.- type silicon epitaxial layer, 2 represents a LOCOS oxide film, 3 represents a silicon oxide layer, 4 represents a boron-doped polysilicon layer, 5 represents a silicon oxide layer, 6 represents an opening, 7 represents a p-type base region, 8 represents a boron-doped polysilicon side wall, 9 represents a silicon oxide side wall, 10 represents a polysilicon layer, 11 represents an n-type emitter region, 12 represents an opening for a base electrode, 13 represents an emitter electrode and 14 represents a base electrode.
An example of a structure of a conventional self-alignment type bipolar transistor as well as a manufacturing process thereof will be described based on this figure.
First, as a first process, an n.sup.+ type buried layer 16 for reducing series resistance of a collector on a silicon substrate 15 is formed, and an n.sup.- type silicon epitaxial layer 1 having a thickness of approximately 1 .mu.m is formed thereafter.
As a second process, a silicon nitride (Si.sub.3 N.sub.4) layer not illustrated is formed in an element forming region on the n.sup.- type silicon epitaxial layer 1, and the n.sup.- type silicon epitaxial layer 1 is oxidized thermally with the silicon nitride layer as a mask, thereby to form the LOCOS oxide film (SiO.sub.2) 2.
Further, n-type impurities are diffused from a collector contact portion where the LOCOS oxide film 2 is not formed, thereby to form an n.sup.+ type diffused region 17 in the depth of reaching the n.sup.+ type buried layer 16 described above. This n.sup.+ type diffused region 17 serves as a current passage of a contact layer.
As a third process, the silicon oxide layer 3 having a thickness of approximately 2,000 .ANG. is formed on the whole surface by a CVD method and the boron (B) doped polysilicon layer 4 having a thickness of 3,000 .ANG. is formed thereon, and thereafter, unnecessary portions except those for pulling out an electrode from the base region are removed by patterning.
Then, the silicon oxide layer 5 having a thickness of approximately 3,000 to 4,000 .ANG. is formed on the whole surface by a CVD method.
As a fourth process, the opening 6 penetrating through the silicon oxide layer 5, the boron-doped polysilicon layer 4 and the silicon oxide layer 3 is formed on the base region by a photolithography technique.
As a fifth process, after a thin boron-doped polysilicon layer is formed on the whole surface by a CVD method, resist is applied thereon, and the resist is etched back to be left so as to be buried in a recessed portion of the thin boron-doped polysilicon layer formed along the inner periphery of the opening 6. Thereafter, the exposed portion of this thin boron-doped polysilicon layer is removed by anisotropic etching with the buried resist as a mask, and over-etching of about 2000 to 3000 .ANG. is performed further. Furthermore, the resist inside the opening 6 is removed and the boron-doped polysilicon layer remaining in the opening 6 is etched by RIE, thereby to form the side wall 8 composed of boron-doped polysilicon which is lower than the upper edge of the opening 6, and also to expose a part of the n.sup.- type silicon epitaxial layer 1 from the opening 6.
Next, as a sixth process, ions of p-type impurities are implanted into the n.sup.- type silicon epitaxial layer 1 through the opening 6 so as to form the inside of the base region 7, and on the other hand, boron impurities of the doped polysilicon layer 4 are diffused into the n.sup.- type silicon epitaxial layer 1 by heat treatment through the side wall 8, thereby to form the outside of the base region 7.
As a seventh process, a thick silicon oxide layer is formed on the whole surface by a CVD method and the silicon oxide side wall 9 is formed by anisotropic etching such as RIE, and an opening 6a is also formed for exposing the base region 7 at a portion surrounded by the side wall 9.
The polysilicon layer 10 is formed by a CVD method along the side wall 9 of the silicon oxide in the opening 6 and the surface of the base region 7, As ions are implanted into this polysilicon layer 10 and heat treatment is applied thereto, thereby to form the n-type emitter region 11 in the upper layer portion of the base region 7.
Since the conductive side wall 8 composed of boron-doped polysilicon has been formed lower than the upper edge of the opening 6 previously, the insulating side wall 9 composed of silicon oxide is formed covering the conductive side wall 8 in a sufficient thickness. Thus, the conductive side wall 8 and the polysilicon layer 10 will never be short-circuited with each other.
As an eighth process, the opening 12 for a base electrode is formed in the silicon oxide layer 5 in the vicinity of the opening 6, and an opening 18 for collector contact is formed further. Thereafter, an Al film is formed on the whole surface, and the emitter electrode 13, the base electrode 14 and a collector electrode 19 are formed by applying patterning thereto.
The technique of such a bipolar transistor is described in a document of International Electron Devices Meeting 1992 p.445-p.448 for instance.
In a bipolar transistor improved as described above, a remarkable high speed is attainable as compared with a bipolar transistor in existence before then.
However, the demands of the times for a high speed is very strong, and realization of a bipolar transistor further made higher in speed is looked forward to. In order to make a bipolar transistor further higher in speed, it is required to give consideration to the following points.
In order to realize a high speed of a bipolar transistor, it is required to reduce a base region and an emitter region, to decrease pn junction parasitic capacities being parasitic between the base region and the collector region and between the base region and the emitter region, respectively, and to decrease parasitic resistances being parasitic in the base region and the emitter region. By decreasing these parasitic capacities and parasitic resistances, shortening of lag time due to charge and discharge of parasitic capacities can be aimed at, thus making it possible to achieve a high speed of the operation.
In the above-described bipolar transistor, however, such problems as described in following articles (1) to (3) are generated when it is intended to simply reduce the base region 7 and the emitter region 11.
(1) In order to form a fine opening in a silicon oxide layer, a polysilicon layer or the like on the base region and the emitter region, it is required to develop a photoresist material having high resolution and exposure techniques of high accuracy of the next generation. PA1 (2) The finer the opening for the emitter region becomes, the more difficult it becomes to form the opening stably. PA1 (3) Even if the opening 6a for the emitter region is formed with high accuracy, various problems described hereunder are generated when the opening 6a becomes extremely small.
The size of the opening 6a on the emitter region 11 is obtained by subtracting two times of the thickness in the width direction of the side wall 8 composed of polysilicon and two times of the thickness in the width direction of the insulating side wall 9 from the size of the opening 6 above the base region 7 formed at the beginning by exposure techniques.
As a result, the size of the opening 6a above the emitter region 11 becomes non-uniform due to dispersion of film thickness of the opening 6, the polysilicon side wall 8 and the insulating side wall 9 therearound.
In particular, in case the width of the opening 6a above the emitter region 11 was defined by the polysilicon side wall 8 and the insulating side wall 9 which are buried therein, it is liable to be affected by dispersion of the widths of the opening 6, the polysilicon side wall 8 and the insulating side wall 9. Therefore, a problem that the opening 6a above the emitter region is not opened also occurs in the worst case. Therefore, the smaller the opening 6a above the emitter region 11 becomes, the more difficult it becomes to show the opening 6a always stably.
Sectional views for explaining the problems of a conventional very small opening 6a for an emitter region are shown in FIG. 2(A) and FIG. 2(B). In these figures, reference numerals same as those in FIG. 1 show the same parts as in FIG. 1 except that configurations and sizes are different.
First, as shown in FIG. 2(B), the silicon oxide layer 2, the boron-doped polysilicon layer 4 and the silicon oxide layer 5 are deposited on the n.sup.- type silicon epitaxial layer 1, and an opening 6 having a small diameter which penetrates through these three layers from the top is formed. When a base-region 7 is formed by introducing impurities through the opening 6 and a boron-doped polysilicon side wall 8 and a side wall 9 composed of silicon oxide are formed in the opening 6 thereafter, a finer opening 6a for an emitter region in a size b obtained by subtracting two times of the widths of the side wall 8 composed of boron-doped polysilicon and the side wall 9 composed of silicon oxide from the width a of the opening 6.
Normally, in a bipolar transistor, a thin polysilicon layer is inserted inbetween an emitter diffused layer and an emitter metal electrode. The reason for the above is for preventing erosion of a reactant by eutectic alloy reaction between the emitter diffused layer and the emitter metal electrode into the diffused region.
In the formation of polysilicon by a CVD method performed normally, however, since entry of polysilicon into openings is excellent, the inside of the emitter opening 6a is buried completely by a polysilicon layer 10 as shown in FIG. 2(A) when the emitter width is narrowed. Then, impurities are introduced through the polysilicon layer 10 so as to form an emitter region 11 and to further form an emitter electrode 13 thereon.
However, the specific resistance of doped polysilicon is larger than that of a metal, and the doped polysilicon layer 10 formed in the fine opening 6a for an emitter region becomes slender as shown in FIG. 2(A). Therefore, the resistance from the emitter region 11 to the emitter electrode 13 becomes large, thus being unable to realize a high-speed bipolar transistor.
So, as shown in FIG. 2(B), the polysilicon layer 10 is not buried completely in the emitter opening 6a, but is formed very thin so as to have an almost equal thickness along the inner periphery of the opening 6a. Furthermore, it is sufficient that a low-resistance metal such as Al is deposited or sputtered in the opening 6a thereby to form an emitter electrode 13.
However, in this case, since entry of the metal into the opening 6a above the narrow emitter region 11 is poor, the metal does not fill the inside of the opening 6a, but is accumulated on the peripheral portion thereof. Thus, the very thin doped polysilicon layer 10 acts as an emitter electrode from the emitter diffused layer 11 up to the top of the opening 6a. Hence, the resistance becomes substantially high.
In order to suppress the resistance from the emitter region to the emitter electrode not to become high, the smallest width portion of the opening has to be approximately 0.8 .mu.m, and the width of the emitter region formed below the opening becomes approximately 0.2 .mu.m. In a bipolar transistor in this size, however, the parasitic capacity as described above cannot be reduced.